JPH0217976B2 - - Google Patents

Info

Publication number
JPH0217976B2
JPH0217976B2 JP56144476A JP14447681A JPH0217976B2 JP H0217976 B2 JPH0217976 B2 JP H0217976B2 JP 56144476 A JP56144476 A JP 56144476A JP 14447681 A JP14447681 A JP 14447681A JP H0217976 B2 JPH0217976 B2 JP H0217976B2
Authority
JP
Japan
Prior art keywords
phase
clock
output
received data
delay section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56144476A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5846743A (ja
Inventor
Kuniaki Uchiumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56144476A priority Critical patent/JPS5846743A/ja
Publication of JPS5846743A publication Critical patent/JPS5846743A/ja
Publication of JPH0217976B2 publication Critical patent/JPH0217976B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56144476A 1981-09-11 1981-09-11 位相同期装置 Granted JPS5846743A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56144476A JPS5846743A (ja) 1981-09-11 1981-09-11 位相同期装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56144476A JPS5846743A (ja) 1981-09-11 1981-09-11 位相同期装置

Publications (2)

Publication Number Publication Date
JPS5846743A JPS5846743A (ja) 1983-03-18
JPH0217976B2 true JPH0217976B2 (en]) 1990-04-24

Family

ID=15363181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56144476A Granted JPS5846743A (ja) 1981-09-11 1981-09-11 位相同期装置

Country Status (1)

Country Link
JP (1) JPS5846743A (en])

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6128251A (ja) * 1984-07-19 1986-02-07 Nitsuko Ltd クロツク同期方式
JPS63310217A (ja) * 1987-06-12 1988-12-19 Nitsuko Corp ディジタル位相同期回路
JPH0616620B2 (ja) * 1987-06-15 1994-03-02 沖電気工業株式会社 ディジタル位相同期回路

Also Published As

Publication number Publication date
JPS5846743A (ja) 1983-03-18

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